1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, NAND type flash memories have been commonly used as electrically erasable nonvolatile semiconductor storage devices. The NAND type flash memory includes a large number of NAND cell units. Each NAND cell unit is configured so that a plurality of memory cells connected together in series are provided between select transistors. A control gate line (word line) is connected to each memory cell. A select gate line is connected to each select transistor.
In the NAND type flash memory, each of the select gate lines is wider than each of the control gate lines. That is, the control gate lines are arranged at the same pitch, and the select gate lines are arranged at a pitch different from that of the control gate lines. Thus, the select gate lines disturb the periodicity of the line arrangement. As a result, a decrease in the size of the semiconductor device affects the resolution or margin in a lithography step. This makes it difficult to accurately form the patterns of select gate lines and control gate lines.
Jpn. Pat. Appln. KOKAI Publication No. 2003-51557 discloses a structure in which two select gate lines having the same line width as that of control gate lines are provided in place of one select gate line with a large line width. This structure enables the select gate lines to be arranged at the same pitch as that of the control gate lines.
However, in this proposal, the two select gate lines are connected together using only a conductive portion that contacts the top surfaces of both select gate lines. That is, the two select gate lines are separated from each other. Accordingly, in the areas of the two select gate lines other than those in which the connecting conductive portion is formed, separate control signals propagate through the two select gate lines. Thus, disadvantageously, operational timings for the two select transistors corresponding to the two select gate lines may deviate from each other. This may prevent high-speed operations.
Thus, problems with the conventional art are that it is difficult to accurately form patterns and that the operational timings for the two select transistors may deviate from each other to prevent appropriate desired operations.